Regviz

Espressif Systems /ESP32-P4 /LP_AON_CLKRST /LP_AONCLKRST_RESET_CAUSE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LP_AONCLKRST_RESET_CAUSE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/LP_AON_CLKRST/LP_AONCLKRST_RESET_CAUSE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LP_AONCLKRST_LPCORE_RESET_CAUSE 0 (LP_AONCLKRST_LPCORE_RESET_FLAG)LP_AONCLKRST_LPCORE_RESET_FLAG 0LP_AONCLKRST_HPCORE0_RESET_CAUSE 0 (LP_AONCLKRST_HPCORE0_RESET_FLAG)LP_AONCLKRST_HPCORE0_RESET_FLAG 0LP_AONCLKRST_HPCORE1_RESET_CAUSE 0 (LP_AONCLKRST_HPCORE1_RESET_FLAG)LP_AONCLKRST_HPCORE1_RESET_FLAG 0 (LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK)LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK 0 (LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR)LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR 0 (LP_AONCLKRST_LPCORE_RESET_FLAG_CLR)LP_AONCLKRST_LPCORE_RESET_FLAG_CLR 0 (LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR)LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR 0 (LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR)LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR 0 (LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR)LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR 0 (LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR)LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR

Description

need_des

Fields

LP_AONCLKRST_LPCORE_RESET_CAUSE

6’h1: POR reset 6’h9: PMU LP PERI power down reset 6’ha: PMU LP CPU reset 6’hf: brown out reset 6’h10: LP watchdog chip reset 6’h12: super watch dog reset 6’h13: glitch reset 6’h14: software reset
LP_AONCLKRST_LPCORE_RESET_FLAG

need_des
LP_AONCLKRST_HPCORE0_RESET_CAUSE

6’h1: POR reset 6’h3: digital system software reset 6’h5: PMU HP system power down reset 6’h7: HP system reset from HP watchdog 6’h9: HP system reset from LP watchdog 6’hb: HP core reset from HP watchdog 6’hc: HP core software reset 6’hd: HP core reset from LP watchdog 6’hf: brown out reset 6’h10: LP watchdog chip reset 6’h12: super watch dog reset 6’h13: glitch reset 6’h14: efuse crc error reset 6’h16: HP usb jtag chip reset 6’h17: HP usb uart chip reset 6’h18: HP jtag reset 6’h1a: HP core lockup
LP_AONCLKRST_HPCORE0_RESET_FLAG

need_des
LP_AONCLKRST_HPCORE1_RESET_CAUSE

6’h1: POR reset 6’h3: digital system software reset 6’h5: PMU HP system power down reset 6’h7: HP system reset from HP watchdog 6’h9: HP system reset from LP watchdog 6’hb: HP core reset from HP watchdog 6’hc: HP core software reset 6’hd: HP core reset from LP watchdog 6’hf: brown out reset 6’h10: LP watchdog chip reset 6’h12: super watch dog reset 6’h13: glitch reset 6’h14: efuse crc error reset 6’h16: HP usb jtag chip reset 6’h17: HP usb uart chip reset 6’h18: HP jtag reset 6’h1a: HP core lockup
LP_AONCLKRST_HPCORE1_RESET_FLAG

need_des
LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK

1’b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1’b1: disable lpcore pmu_lp_cpu_reset reset_cause
LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR

need_des
LP_AONCLKRST_LPCORE_RESET_FLAG_CLR

need_des
LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR

need_des
LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR

need_des
LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR

need_des
LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR

need_des

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data